1. Field of the Invention
The present invention pertains to a buffer design for use in digital signal processing applications where reduction in microchips size is an important consideration. More particularly, the present invention relates to a compact buffer design employing parallel registers and providing serial input and serial output of data.
2. Description of the Related Art
In digital signal processing applications, digital data is provided directly and indirectly to and from a digital signal processor (DSP) in either a parallel format or a serial format. Typically, data is converted between a parallel format and a serial format by utilizing a serial input and output (SIO) interface. As an alternative to an SIO, a serial shift buffer register may be implemented.
Both of the above-mentioned devices have drawbacks. In particular, both the serial shift buffer register and the SIO are relatively large in a physical sense due to the wiring required for connecting together the serial shift registers implemented in such devices and, consequently, occupy a large chip area. In the case of a serial shift register or an SIO manufactured on a common digital chip with a DSP, the relatively large size of the SIO or serial shift register decreases chip yield, i.e. fewer chips are produced per wafer or substrate. For a mixed signal chip receiving both analog and digital signals, the relatively large sizes of the SIO and serial shift registers result in a larger chip and a correspondingly higher manufacturing cost per unit area due to the masking steps involved in production. Moreover, the interrupt frequency associated with a DSP reading from and writing to an SIO is relatively high, reducing the overall processing speed of a system employing the DSP and SIO components.